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fn9241 rev 0.00 page 1 of 11 october 4, 2005 fn9241 rev 0.00 october 4, 2005 ISL9200 charging system safety circuit datasheet the ISL9200 is an integrated circuit (ic) optimized to provide a li-ion battery redundant safet y protection from failures of a charging system. the ic monito rs the input voltage, the battery voltage, and the char ge current. when any of the three parameters exceeds its limit, the ic turns off an interna l p-channel mosfet to remove the power from the charging system. in addition t o the above protect ed parameters, the ic also monitors its own internal temperature and turns off the p-channel mosfet when the die temperature exceeds 140c. together with the ba ttery charger ic and the protection module in a battery pack, t he charging system using the ISL9200 has triple-level protection and is two-fault tolerant. the ic is designed to turn on the intern al pfet slowly to avoid inrush current at power-up but will turn off the pfet quickly when input overvoltage is detected, in order to remove the power before any damage occurs. the ISL9200 has a logic warning output to i ndicate the fault and an enable input to allow the system to remo ve the input power. typical application circuit features ? fully integrated protection circuit for three protection variables - user programmable overcurre nt protectio n threshold - input overvoltage protec tion in less than 1s - battery overvoltage protection ? high immunity of false triggering under transients ? high accuracy protection thresholds ? warning output to indicat e the occurrence of faults ? enable input ? thermal enhanced dfn package ? pb-free plus anneal available (rohs compliant) applications ? cell phones ? digital still cameras ? pdas and smart phones ? portable instruments ? desktop chargers related literature ? technical brief tb363 guidelines for handling and processing moisture sensit ive surface mount devices (smds) ? technical brief tb379 th ermal characterization of packaged semiconductor devices ? technical brief tb389 pcb land pattern design and surface mount guidelines for qfn packages ordering information part # part marking temp. range (c) package pkg. dwg. # ISL9200irz* (note) 00z -40 to 85 12 ld 4x3 dfn (pb-free) l12.4x3 ISL9200eval1 ISL9200 evaluation board *add -t suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/d ie attach materials and 100% matte tin plate termination finish, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. input isl6292 battery charger r vb c 1 r ilim battery pack ISL9200 ilim wrn vin gnd vb out en + pinout ISL9200 (4x3 dfn) top view note: epad must be electric ally connected to the gnd pin. vin vin gnd wrn out ilim vb nc out nc nc en 2 3 4 1 5 11 10 9 12 8 6 7 epad
ISL9200 fn9241 rev 0.00 page 2 of 11 october 4, 2005 absolute maximum ratings (reference to gnd) thermal information supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30v output and vb pin (out, vb) (note 1) . . . . . . . . . . . . . . . -0.3 to 7v other pins (ilim, wrn , en ) . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5v esd rating human body model (per jesd22-a114-b) . . . . . . . . . . . . .3 000v machine model (per eia/jesd22 a115-a) . . . . . . . . . . . . . .200v recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . .-40c to 85c supply voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3v to 6.5v thermal resistance (notes 2, 3) ? ja (c/w) ? jc (c/w) 4x3 dfn package . . . . . . . . . . . . . . . . 41 3.5 maximum junction temperat ure (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. the maximum voltage rating for the vb pin under continuous op erating conditions is 5.5v. all other pins are allowed to opera te continuously at the absolute maximum ratings. 2. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 3. ? jc , case temperature location is at the center of the exposed m etal pad on the package underside. see tech brief tb379. electrical specifications typical values are tested at vin = 5v and 25c ambient temperat ure, maximum and minimum values are guaranteed over the recommended oper ating conditions, unless ot herwise noted. parameter symbol test conditions min typ max units power-on reset rising vin threshold v por 2.4 2.58 2.7 v por hysteresis - 100 - mv vin bias current i vin when enabled 0.75 0.9 1.05 ma vin bias current when disabled 30 60 100 ? a protections input overvoltage protection (ovp) v ovp 6.65 6.8 7.0 v input ovp hysteresis - 60 100 mv input ovp falling threshold 6.55 - - v input ovp propagation delay --1 ? s overcurrent protection i ocp v vb = 3v, r ilim = 25k ? 0.93 1.0 1.07 a overcurrent protection blanking time bt ocp - 170 - ? s battery overvoltage protection threshold v bovp 4.325 4.4 4.475 v battery ovp threshold hysteresis 75 - mv battery ovp falling threshold 4.225 - - v battery ovp blanking time bt bovp 180 - ? s vb pin leakage current v vb = 4.4v - 20 na over temperature protection rising threshold 140 - c over temperature protection falling threshold - 90 - c logic en input logic high 1.5 - - v en input logic low --0.4v en internal pull down resistor 100 200 400 k ? wrn output logic low sink 5ma current - 0.35 0.8 v wrn output logic high leakage current - - 1 ? a power mosfet on resistance r ds(on) measured at 500ma, 4.3v < v in < 6.5v - 250 450 m ?
ISL9200 fn9241 rev 0.00 page 3 of 11 october 4, 2005 pin descriptions vin (pins 1, 2) the input power source. the vin can withstand 30v input. gnd (pin 3) system ground reference. wrn (pin 4) wrn is an open-drain logic output that turns low when any protection event occurs. nc (pins 5, 6, 12) no connection and mus t be left floating. en (pin 7) enable input. pull this pin to low or leave it floating to enab le the ic and force it to high to disable the ic. vb (pin 8) battery voltage monitoring input. this pin is connected to the battery pack positive terminal v ia an isolation resistor. ilim (pin 9) overcurrent protection thres hold setting pin. connect a resistor between this pin and gnd to set the ocp threshold. out (pins 10, 11) output pin. epad the exposed pad at the bottom of the dfn package for enhancing thermal performanc e. must be electrically connected to t he gnd pin. typical applications block diagram input isl6292 battery charger r vb c 1 r ilim battery pack ISL9200 ilim wrn vin gnd vb out en part description r ilim 25k ? r vb 200k ? to 1m ? c1 1f/16v x5r ceramic capacitor + figure 1. block diagram por pre-reg ref vin vb gnd 1. 2v 0. 8v r 1 r 2 q 1 input cp1 i sl6292 bat t ery charger cp2 out r ilim ilim fet dri ver ea r 3 r 4 r vb cp3 q 2 q 3 buf wrn q 4 logic en q 5 r 5 +
ISL9200 fn9241 rev 0.00 page 4 of 11 october 4, 2005 typical operating performance the test conditions for the typica l operating performance are: v in = 5v, t a = 25c, r ilim = 25.5k ? , r vb = 200k ? , unless otherwise noted. figure 2. captured waveforms for power-up. the output is loaded with a 10 ? resistor figure 3. captured waveforms when the input voltage steps from 6.5v to 10.5v figure 4. captured waveforms when the input gradually rises to the input overvoltage threshold figure 5. transient when the input voltage steps from 7.5v to 6.5v figure 6. transient waveforms when input steps from zero to 9v figure 7. battery overvoltage protection. the ic is latched off after 16 counts of protection. vb voltage varies between 4.3v to 4.5v vin (1v/div) out (1v/div) load current (200ma/div) time: 5ms/div vin (2v/div) out (2v/div) wrn (5v/div) time: 2 ? s/div vin (2v/div) time: 200ms/div out (2v/div) wrn (5v/div) vin (2v/div) time: 5ms/div out (2v/div) wrn (5v/div) vin (2v/div) out (2v/div) time: 500 ? s/div wrn (5v/div) ilim (1v/div) vin (1v/div) time: 20s/div out (1v/div) wrn (5v/div) vb (1v/div)
ISL9200 fn9241 rev 0.00 page 5 of 11 october 4, 2005 figure 8. power-up waveforms when output is short-circuited figure 9. zoomed-in view of figure 8 (blue: load current; pink: out pin voltage) figure 10. input bias current vs input voltage when enabled and disabled figure 11. input bias current at different input voltages when en abled and disabled figure 12. v por vs temperature figure 13. input overvoltage protection thresholds vs temperature typical operating performance the test conditions for the typica l operating performance are: v in = 5v, t a = 25c, r ilim = 25.5k ? , r vb = 200k ? , unless otherwise noted. (continued) vin (1v/div) out (1v/div) load current (500ma/div) wrn (5v/div) time: 200ms/div vin (1v/div) out (1v/div) load current (500ma/div) wrn (5v/div) time: 10ms/div 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 35 input voltage (v) input bias current (a) enabled disabled 0 100 200 300 400 500 600 700 800 900 1000 -50 -20 10 40 70 100 130 temperature (c) current (a) 6.5v/enabled 5v/enabled 4.3v/enabled 30v/enabled 30v/disabled 4.3v/disabled 6.5v/disabled 5v/disabled 2.46 2.48 2.5 2.52 2.54 2.56 2.58 2.6 -50 -20 10 40 70 100 130 v por (v) rising threshold falling threshold temperature (c) 6.65 6.7 6.75 6.8 6.85 6.9 6.95 -50 -20 10 40 70 100 130 v ovp (v) rising threshold falling threshold temperature (c)
ISL9200 fn9241 rev 0.00 page 6 of 11 october 4, 2005 figure 14. overcurrent protection thresholds vs temperature at various input voltages figure 15. overcurrent protection blanking time vs temperature figure 16. overcurrent protection thresholds vs temperature at various input voltages figure 17. battery voltage ovp thresholds vs temperature at various input voltages figure 18. battery ovp blanking time figure 19. vb pin leakage c urrent vs temperature typical operating performance the test conditions for the typica l operating performance are: v in = 5v, t a = 25c, r ilim = 25.5k ? , r vb = 200k ? , unless otherwise noted. (continued) 960 970 980 990 1000 1010 1020 1030 1040 1050 -50 -20 10 40 70 100 130 temperature (c) i ocp (ma) 6.5v 5v 4.3v 3v current limit = 1a 150 155 160 165 170 175 180 185 190 195 200 -50 -20 10 40 70 100 130 bt ocp (s) temperature (c) 470 475 480 485 490 495 500 505 510 515 -50 -20 10 40 70 100 130 i ocp (ma) 4.3v 6.5v 5v 3v temperature (c) 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.4 4.41 4.42 -50 -20 10 40 70 100 130 v bovp (v) rising thresholds for 4.5v, 5v and 6.5v input falling thresholds for 4.5v, 5v and 6.5v input temperature (c) 150 155 160 165 170 175 180 185 190 195 200 -50 -20 10 40 70 100 130 bt bovp (s) temperature (c) 0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -20 10 40 70 100 130 vb pin leakage current (na) tested at 5v temperature (c)
ISL9200 fn9241 rev 0.00 page 7 of 11 october 4, 2005 theory of operation the ISL9200 is an integrated circuit (ic) optimized to provide a redundant safety protection to a li-ion battery from charging system failure s. the ic monitors the input voltage, the battery voltage, and the charge current. when any of the above three parameters exceeds its limit, the ic turns off an internal p-channel mosfet to remove the power from the charging system. in addition to the above protected parameters, the ic also monitors its own internal temperature and tur ns off the p-channel mosfet when the temperature exceeds 140c . together with the battery charger ic and the pr otection module in a battery pack, the charging system has triple-lev el protectio n from over- charging the li-ion battery a nd is two-fault tolerant. the ISL9200 protects up to 30v input voltage. power-up the ISL9200 has a power-on re set (por) threshold of 2.6v with a built-in hyster esis of 100mv. befor e the input voltage reaches the por threshold, the internal power pfet is off. approximately 10ms after th e input voltage exceeds the por threshold, the ic resets itself and begins the soft-start. the 10ms delay allows any trans ients at the input during a hot insertion of the power supply to settle down before the ic starts to operate. the soft-st art slowly turns on the power pfet to reduce the inrush cu rrent as well as the input voltage drop during the transiti on. the power-up behavior is illustrated in figure 2. input overvoltage protection (ovp) the input voltage is monitored by the comparator cp1 in the block diagram (figure 1). cp1 has an accurate reference of 1.2v from the bandgap referenc e. the ovp threshold is set by the resistive divider consisting of r1 and r2. the figure 20. en input threshold vs temperature figure 21. en pin internal pull-down resistance figure 22. on resistance vs temperature at different input volta ges typical operating performance the test conditions for the typica l operating performance are: v in = 5v, t a = 25c, r ilim = 25.5k ? , r vb = 200k ? , unless otherwise noted. (continued) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -20 10 40 70 100 130 en threshold (v) temperature (c) 150 160 170 180 190 200 210 220 230 240 250 -50 -20 10 40 70 100 130 en pin internal pull-down (k ? ) temperature (c) 0 0.1 0.2 0.3 0.4 0.5 -50 -20 10 40 70 100 130 r ds(on) ( ? ) 3v 4.3v 5v 6.5v temperature (c)
ISL9200 fn9241 rev 0.00 page 8 of 11 october 4, 2005 protection threshold is set to 6.8v. when the input voltage exceeds the threshold, the cp1 outputs a logic signal to turn off the power pfet within 1s ( see figure 3) to prevent the high input voltage from damag ing the electronics in the handheld system. the hysteresis for the input ovp threshold is given in the electrical specification. when the input overvoltage condition is removed, the ISL9200 re- enables the output by running th rough the soft-start, as shown in figure 5. because of the 10ms second delay before the soft-start, the outpu t is never enabled if the input rises above the ovp threshold quickly, as shown in figure 6. battery overvoltage protection the battery voltage ovp is realized with the vb pin. the comparator cp3, as shown in figure 1, monitors the vb pin and issues an overvoltage si gnal when the battery voltage exceeds the 4.4v battery ovp threshold. the threshold has 75mv built-in hysteresis. the co mparator cp3 has a built-in 180s blanking time to preven t any transient voltage from triggering the ovp. if the ovp situation st ill exists after the blanking time, the power pfet is turned off. the control logic contains a 4-bit binary counter that if the battery overvoltage event occurs 16 times, the power pfet is turned off permanently , as shown in figur e 7. recycling the input power or toggling the enable (en ) input will reset the counter and restart the ISL9200. the resistor between the vb pin and the battery, r vb , as shown in the typical applicatio ns circuit, is an important component. this resistor provid es a current limit in case the vb pin is shorted to the input v oltage under a failure mode. the vb pin leakage current under normal operation is negligible to allow a resistance of 200k ? to 1m ? be used. overcurrent protection (ocp) the current in the power pfet is limited to prevent charging the battery with an excessive c urrent. the current is sensed using the voltage drop across the power fet after the fet is turned on. the reference of t he ocp is generated using a sensing fet q2, as shown in figure 1. the current in the sensing fet is forced to the v alue programmed by the ilim pin. the size of the power fet q1 is 31,250 times the size of the sensing fet. therefore, when the current in the power fet is 31,250 times the current in the sensing fet, the drain voltage of the power fet falls below that of the sensing fet. the comparator cp2 t hen outputs a signal to turn off the power fet. the ocp threshold can be calculated us ing the following equation: where the 0.8v is the regulated voltage at the ilim pin. the ocp comparator cp2 has a bu ilt-in 170s del ay to prevent false triggering by transient s ignals. the ocp function also has a 4-bit binary counter tha t accumulates during an ocp event. when the total count re aches 16, the power pfet is turned off permanently unless the input power is recycled or the enable pin is toggled. figure 8 and figure 9 illustrate the waveforms during the power-u p when the output is short- circuited to ground. internal over temperature protection the ISL9200 monitors its ow n internal temperature to prevent thermal failures. w hen the internal temperature reaches 140c, the ic turn s off the p-channel power mosfet. the ic does not re sume operation until the internal temperature drops below 90c. external enable control the ISL9200 offers an enable (en ) input. when the en pin is pulled to logic high, the pr otection ic is shut down. the internal control circuit as well as the power pfet are turned off. both 4-bit binary counter s for the battery ovp and the ocp are reset to zero when the ic is re-enabled. the en pin has an internal 200k ? pull-down resistor. leaving the en pin floating or driving it to below 0.4v enables the ic. warning indication output the wrn pin is an open-drain output that indicates a low signal when any of the three protection events happens. this allows the microprocessor to give an indication to the user to further enhance the safety of the charging system. applications information the ISL9200 is designed to meet the lithium-safe criteria when operating toget her with the isl6292 family li-ion battery chargers. the lithiu m-safe criteria requires the charger output to fall withi n the green region shown in figure 23 under normal operating conditions and not to fall in the red region when there is a single fault in the charging system. taking into account the safety circui t in a li-ion battery pack, the charging syst em is allowed to have two faults without creating hazardou s conditions for the battery cell. the output of any isl6292 family chargers, such as the isl6292c, has a typical i-v cu rve shown with the blue lines under normal operation, which i s within the green region. the function of the isl9 200 is to add an redundant protection layer such that, under any single fault condition, the charging system o utput does n ot exceed t he i-v limits shown with the red lines. as a result, the cha rging system adopting the ISL9200 and the isl6292c chip set can easily pass the lithium-safe criteria test procedures. the ISL9200 is a simple devic e that requires only three external components, in addition to the isl6292 charger circuit, to meet the lithium-saf e criteria, as shown in the typical application circuit. the selection of the current limit resistor r ilim is given in the overcurre nt protection section. i lim 0.8v r ilim --------------- 31250 25000 r ilim ---------------- = ? =
ISL9200 fn9241 rev 0.00 page 9 of 11 october 4, 2005 r vb selection the r vb prevents a large current from the vb pin to the battery terminal, in case the ISL9200 fails. the recommended value should be between 200k ? to 1m ? . with 200k ? resistance, the worst cas e current flowing from the vb pin to the charger output is, (30v - 4.2v)/200k ? = 130 ? a, assuming the vb pin voltage is 30v under a failure mode and the battery voltage is 4.2v . such a small current can be easily absorbed by the bias c urrent of other components in the handheld system. increasing the r vb value reduces the worst case current, but at the same time increases the error for the 4.4v batte ry ovp threshold. the error of the battery ovp threshold is the original accuracy at the vb pi n given in the electrical specification plus the voltage built across the r vb by the vb pin leakage current. the vb pin leakage c urrent is less than 20na, as given in the electrical specification. with the 200k ? resistor, the worst-case additional error is 4mv and with a 1m ? resistor, the worst-case a dditional error is 20mv. interfacing to mcu the ISL9200 has the enable (en ) and the warning (wrn ) digital signals that can be interfaced to a microcontroller uni t (mcu). both signals can be left floating if n ot used. when interfacing to an mcu, it is h ighly recommended to insert a resistor between the ISL9200 signal pin and the mcu gpio pin, as shown in figure 24. the resistor creates an isolation to limit the current, in case a h igh voltage shows up at the ISL9200 pins under a failu re mode. the recommended resistance ranges from 10k ? to 100k ? . the selection of the r en is dependent on the io vol tage (vio) o f the mcu. r en should be selected so that the ISL9200 en pin voltage is above the disable threshold when the gpio output of the mcu is high. capacitor selection the input capacitor (c 1 in the typical application circuit) is for decoupling. higher value reduces the voltage drop or the over shoot during transients. two scenarios can cause the input voltage over shoot. the first one is when the ac adap ter is inserted live (hot insertion) and the second one is when the current in the power pfet of the ISL9200 has a step-down change. figure 25 shows an equivalent circuit for the ISL9200 input. the cable between the ac/dc c onverter output and the handheld system input has a parasitic inductor. the parasitic resistor is the lumped sum of various components, such as the cable, the adapter output capacitor esr, the connector contact resistance, and so on. during the load current step- down transient, the energy stored in the parasitic inductor is used to charge the input decoupling capacitor c2. the ISL9200 is designed to turn off the power pfet slowly durin g the ocp, the battery ovp event, and when the devic e is disabled via the en pin. because of such design, the i nput over shoot during those events is not significant. during an input ovp, however, the pfet is turned in less than 1s and can lead to significant over shoot. higher capacitanc e reduces this type of over shoot. figure 23. lithium-sa fe operating regions 5 0 1000 battery voltage (v) charg e current (ma) 12 34 i sl 9200 limits i sl 6292c limits 6 figure 24. digital signal interface between ISL9200 and mcu wrn r 5 q 4 q 5 en ISL9200 mcu r pu r wrn r en vio figure 25. equivalent circuit for the ISL9200 input ac/ dc ISL9200 adapt er cabl e handhel d syst em c1 l r c2
fn9241 rev 0.00 page 10 of 11 october 4, 2005 ISL9200 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. the over shoot caused by a hot insertion is not very dependent on the decoupling capacitance value. especially when ceramic type capacitors are used for decoupling. in theory, the over shoot can rise up to twic e of the dc output voltage of the ac adapter. the actual peak voltage is dependent on the damping factor that is mainly determined by the parasitic resis tance (r in figure 25). in practice, the input decoup ling capacitor is recommended to use a 16v x5r dielectric ceramic capacitor with a value between 0.1f to 1f. the output of the ISL9200 and the input of the charging circuit typically share one decoupling capacitor. the selection of that capacitor i s mainly determined by the requirement of the charging cir cuit. when using the isl6292 family chargers, a 1f, 6.3v, x5r capacitor is recommended. layout recommendation the ISL9200 uses a thermally enhanced dfn package. the exposed pad under the package should be connected to the ground plane electrically as well as thermally. a grid of 1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5 vias per row is recommended (refer to the ISL9200eval1 evaluation board layout). the vias should be about 0.3mm to 0.33mm in diameter. use som e copper on the component layer if possible to further i mprove the therma l performance but it is not mandatory. since the ISL9200 is a protect ion device, the layout should also pay attention to the spacing betwe en tracks. when the distance between the edges o f two tracks is less than 0.76mm, an fmea (failure mec hanism and effect analysis) should be performed to ensur e that a short between those two tracks does not lead to t he charger output exceeding the lithium-safe region limits. intersil will have the fmea document for the solution u sing the ISL9200 and the isl6292c chip set but the layout fmea should be added as part of the analysis.
ISL9200 fn9241 rev 0.00 page 11 of 11 october 4, 2005 dual flat no-lead plastic package (dfn) c // l c e terminal tip for even terminal/side nx (b) section "c-c" 5 (a1) bottom view a 6 area index c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k l l12.4x3 12 lead dual flat no-lead plastic package (compliant to jedec mo-229-vged-4 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.23 0.30 5,8 d 4.00 bsc - d2 3.15 3.30 3.40 7,8 e 3.00 bsc - e2 1.55 1.70 1.80 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n122 nd 6 3 rev. 1 2/05 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see in tersil technical brief tb389.

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